KiCad design review checklist: schematic and PCB

ERC and DRC tell you when a rule is broken. They don't tell you that the reset pin floats, that the regulator has no output capacitor, or that half of your I²C bus is labelled SDA and the other half SDA1. This checklist covers what an experienced reviewer looks at in a KiCad project before the boards are ordered.

1. Before the review

• Annotate the schematic: no R? references left, and references are unique across hierarchical sheets.
• Run Update PCB from Schematic (F8) so the board and schematic agree before anyone reviews either.
• Write down the requirements the design must meet: input voltage range, interfaces, current budget, environment. A review checks the design against something.
• Commit the project to git, so review fixes show up as a reviewable diff.

2. Power and regulators

• Every IC supply pin (VDD, VCC, VDDA, VBAT, VDDIO) sits on a rail, and on the right rail for that part's voltage.
• Every ground pin, including exposed pads (EP/PAD), is connected to ground.
• Regulators have the input and output capacitors their datasheet asks for, with the required type (some LDOs are unstable with low-ESR ceramics; others need them).
• The LDO dropout leaves margin at the lowest input voltage. A 3.3 V LDO with 1 V dropout won't regulate from a 4.0 V battery.
• Power symbols are named consistently (+3V3 vs +3.3V creates two rails in KiCad).
• Reverse polarity, inrush and ESD protection exist on external power inputs, rated for the worst case.
• PWR_FLAG marks rails driven from connectors, so ERC's "power input not driven" warnings mean something.

3. Decoupling and bulk capacitance

• Each IC supply pin, or each group of supply pins, has a local bypass capacitor (typically 100 nF), placed next to the pin on the board.
• Analog supplies (VDDA, AVCC) have their own decoupling, often with a ferrite or RC filter from the digital rail.
• Each rail has bulk capacitance (1–10 µF or more) near where current enters or changes quickly.
• Capacitor voltage ratings have margin, and ceramic DC-bias derating is accounted for on high-value small packages.

4. Pins, pull-ups and interfaces

• No CMOS input floats: unused inputs are tied off or the part has documented internal pulls.
• Reset, enable, boot-mode and chip-select pins have a defined state during power-up.
• I²C SDA and SCL have pull-ups, once per bus, sized for the bus capacitance and speed.
• Open-drain outputs (interrupts, alerts, power-good) have pull-ups to the right voltage.
• No two push-pull outputs drive the same net.
• Logic levels match across every connection between parts on different rails, with level shifting where they don't.
• UART TX goes to RX (and the other way round) in every connector pinout.
• Unused pins are marked with a no-connect flag on purpose, not just left unconnected.

5. Net naming and connectivity

• No single-pin nets other than test points and intentional no-connects.
• No label typos that split a net: SDA vs SDA1, MISO vs MIS0.
• Global labels and hierarchical labels connect what you intend across sheets. A hierarchical label also joins same-named local labels on its sheet.
• Bus members map across the hierarchy in the order you expect (D[0..7] into a sheet pin D[8..15] maps position by position).
• Differential pairs are named so KiCad recognizes them (USB_D+/USB_D- or _P/_N).

6. Parts, values and footprints

• Every symbol has a footprint, and the footprint matches the part you will order (package, pitch, pin 1).
• Pin mapping between symbol and footprint is right for the exact package variant, especially for SOT-23 transistors and regulators, where pinouts vary by vendor.
• Values are plausible for the footprint (a 10 µF 50 V capacitor in 0402 is unlikely; a power resistor in 0402 will cook).
• Polarized parts (electrolytics, diodes, LEDs) have polarity marked on the silkscreen and the footprint matches the symbol's polarity.
• DNP parts are intentional and not on a critical path.
• The BOM fields (manufacturer part number, value, tolerance) are filled for every part you will buy.

7. PCB layout and routing

• No unrouted connections (the ratsnest is empty) unless they are intentionally left for zones that haven't been refilled.
• Refill zones (B) before the final DRC: stale fills hide clearance errors and islands.
• Power and high-current nets use track widths sized for their current and allowed temperature rise, and enough vias where they change layer.
• Decoupling capacitors sit next to their pins with a short path to ground.
• Return paths stay continuous under fast signals: no splits in the reference plane under clock, USB or RF lines.
• Crystals sit close to their pins with load capacitors next to them and ground guarding where the vendor recommends it.
• Connectors, mounting holes and the board outline match the enclosure drawing.
• Thermal reliefs on ground pads are right for hand soldering, and thermal vias are present under exposed-pad parts that need them.

8. ERC, DRC and parity

• ERC runs clean, or every remaining warning is understood and excluded with a note.
• DRC uses the fab's real limits (clearance, track width, annular ring, drill) in the board setup or a .kicad_dru file.
• Schematic/PCB parity is clean: no missing or extra footprints, and no pad-net mismatches.
• Triage, don't ignore: a hundred identical warnings often come from one cause worth fixing.

9. Fabrication outputs

• Gerbers and drill files are regenerated after the last change, and checked in a Gerber viewer.
• Pick-and-place and BOM match the board revision and the DNP list.
• Board revision and date are on the silkscreen.